Open Verification Methodology-based verification flow
Based on the IEEE 1800 SystemVerilog standard. Helps teams develop advanced verification environments with higher levels of integration and portability of verification IP. Fully open, supports multiple languages, and scales from block to system and project to project. Works seamlessly with the Cadence metric-driven verification flow and the Cadence
Verification IP portfolio to maximize productivity, project predictability, and quality.
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Metric-driven verification flow
Ensures verification project predictability, productivity, and quality. Uses specifications to create verification plans, performs metrics analysis/reporting, measures progress, and automates verification tasks. Helps teams determine when high-quality verification is achieved. Uses the
Compliance Management System and the Cadence
Verification IP portfolio to simplify the adoption of metric-driven verification.
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Low-power verification flow
Verifies low-power design intent without disrupting the functional verification environment. Integrates low-power verification planning, coverage, and debugging. Supports the Common Power Format.
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Assertion-based verification flow
Allows teams to start verification earlier and remove bugs faster. Captures design intent, detects errors close to the source, provides coverage information, and enables formal analysis. Supports industry-standard languages. Includes unique assertion-based
Verification IP to simplify adoption of assertion-based verification.
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