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| 03 Dec 2008 | Front-End Logic and Constraint Authoring Flow Using Allegro Design Entry HDLThis webinar will focus on the updated flow/use model between Allegro Design Entry HDL and the Constraint Manager.
Event details » | Online (11:00am - 12:00pm PST) | Webinar | PCB Design |
| 03 Dec 2008 | Chip-Package-Board Co-DesignThis webinar will introduce a methodology and flow for cross-team/fabric co-design optimization among IC design, IC package design, and PCB design.
Event details » | Online (7:00am - 8:00am PST) | Webinar | IC Packaging and SiP Design |
| 04 Dec 2008 | Using the OVM and SystemVerilog for Coverage-Driven VerificationThe Open Verification Methodology (OVM) is the only truly open, interoperable, IEEE 1800 SystemVerilog verification methodology. Now is the time to get started with the OVM. Join us for a hands-on workshop on how to build an OVM-based verification environment that leverages coverage-driven verification. This workshop is free and lunch will be provided.
Event details » | Cadence Headquarters EBC, San Jose, CA 9:00am - 4:30pm | Workshop | Functional Verification |
| 04 Dec 2008 | Front-End Logic and Constraint Authoring Flow Using Allegro Design Entry HDLThis webinar will focus on the updated flow/use model between Allegro Design Entry HDL and the Constraint Manager.
Event details » | Online (7:00am - 8:00am PST) | Webinar | PCB Design |
| 06 Dec 2008 | 9th CRY Cadence Corporate Citizenship Challenge (5C's)CRY Cadence Corporate Cricket Challenge, nicknamed 5Cs, is a successful joint initiative of CRY (Child Rights and You) and Cadence that unites corporates for a cause – the cause of India’s underprivileged children.
Event details » | New Delhi, India | Cadence Event | |
| 10 Dec 2008 | RF PCB Design Using Cadence Allegro Technology and Agilent ADSThis webinar will show an RF design flow from Allegro Design Entry HDL to Allegro PCB RF Option with a bi-directional interface to Agilent's ADS environment.
Event details » | Online (7:00am - 8:00am PST) | Webinar | PCB Design |
| 10 Dec 2008 | RF PCB Design Using Cadence Allegro Technology and Agilent ADSThis webinar will show an RF design flow from Allegro Design Entry HDL to Allegro PCB RF Option with a bi-directional interface to Agilent's ADS environment.
Event details » | Online (11:00am - 12:00pm PST) | Webinar | PCB Design |
| 11 Dec 2008 | Minding the Gaps in Design Verification with the Virtuoso PlatformThis webinar will show you how to accelerate design verification and simulation without sacrificing accuracy. It will explore in more detail the most recent technology innovations in the upcoming 7.1 Cadence Virtuoso Multi-mode Simulation release for design verification.
Event details » | Online | Webinar | Custom IC Design |
| 11 Dec 2008 | Encounter Conformal Users AppreciationJoin us to commemorate 10 years of Encounter Conformal success with Conformal R&D and Conformal users at Cadence Headquarters in San Jose.
Event details » | San Jose, CA | Cadence Event | Logic Design |